Verification of Basic Block Schedules Using RTL Transformations
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چکیده
We present an approach to aid in debugging/development of scheduling algorithm implementations. Our technique makes use of a sequence of a correctness-preserving RTL transformation called Register Transfer Split (RTS), to collectively perform the same task as that of a scheduler. Violation of the transformation precondition signals an error and the sequence of RTS transformations applied so far forms a trace which can be used for debugging purposes.
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تاریخ انتشار 2001